1. Field of the Invention
The present invention relates to a semiconductor device and a control method thereof, and more particularly relates to a semiconductor device including a hierarchical data line structure and a control method thereof.
2. Description of Related Art
A semiconductor memory such as a DRAM (Dynamic Random Access Memory) includes a plurality of memory cells configured to be selected by a word line and a bit line, and read data read from a memory cell is output from the bit line to a data terminal through various signal paths. Normally, the signal paths from the bit line to the data terminal are hierarchized, and data transfer is performed via a switch circuit provided between different hierarchical levels.
An example of a semiconductor memory having signal paths that are hierarchized into a sub-data line LIO and a main data line GIO is shown in FIG. 2 of Japanese Patent Application Laid-open No. 2004-234704, in which the sub-data line LIO and the main data line GIO are connected to each other via switch transistors 61 and 62. The switch transistors 61 and 62 are N-channel MOS transistors, and a connection signal IOSW is supplied to gate electrodes of the switch transistors 61 and 62. Therefore, when the connection signal IOSW is the high level, the sub-data line LIO and the main data line GIO are connected to each other, and when the connection signal IOSW is the low level, the sub-data line LIO and the main data line GIO are disconnected from each other.
However, in the semiconductor memory described in Japanese Patent Application Laid-open No. 2004-234704, because a level of the connection signal IOSW swings at full range between the high level and the low level every time connection and disconnection of the sub-data line LIO and the main data line GIO are repeated, there is a problem that it requires a large current to charge and discharge the gate capacitances of the switch transistors 61 and 62. In addition, because the switch transistors 61 and 62 are the N-channel MOS transistors, when transferring a high level signal, there is another problem that a level of a signal after transfer drops down by the amount of a threshold voltage.